This invention relates to a clock producing circuit receiving active and standby clocks, in particular, to a clock producing circuit which is capable of suppressing a phase shift at the time of a change from an active reference clock to a standby reference clock.
Generally, active and standby reference clocks are supplied to a synchronous clock producing circuit used in a synchronous timing control system for an apparatus that high reliability is required. According to such structure, even if the active reference clock disappears (or comes into an abnormal state), the synchronous clock producing circuit is still able to produce an output clock by using the standby reference clock instead of the active reference clock. Thus the synchronous clock producing circuit can supply the output clock to the apparatus even if it can not receive the active reference clock.
However, the standby reference clock does not always correspond to the active reference clock in phase. If the change from the active reference clock to the standby reference clock is performed under the condition that the phase of the standby reference clock does not correspond to that of the active reference clock, the output clock has a phase shift or change at the time of a change from the active reference clock to the standby reference clock.
It is therefore an object of this invention to provide a clock producing circuit capable of suppressing a phase shift of an output clock at the time of a change between reference clocks.
Other object of this invention will become clear as the description proceeds.
According to an aspect of this invention, a clock producing circuit receives first and second reference clocks at first and second input terminals. The clock producing circuit comprises first phase locked loop connected to the first input terminal to receive the first reference clock and to produce a first output clock having first phase according to the first reference clock. A second phase locked loop has a digital filter with filter coefficients and is connected to the second input terminal to receive the second reference clock and to produce a second output clock having second phase according to the second reference clock. A comparing portion is connected to the first phase locked loop and the second phase locked loop to compare the first phase with the second phase and to supply a filter coefficient control signal representative of difference between the first phase and the second phase to the digital filter. The digital filter updates the filter coefficients according to the filter coefficient control signal so as to reduce the difference between the first phase and the second phase.
According to another aspect of this invention, a clock producing circuit has first and second phase locked loops to produce first and second output clocks according to first and second reference clocks. The clock producing circuit comprises a subsidiary phase comparator connected to the first and second phase locked loops to compare phase of the first output clock with that of the second output clock and to produce a subsidiary comparison signal representing phase difference between the first and second output clocks. A phase adjusting portion is included in the second phase locked loop and connected to the subsidiary phase comparator to adjust phase of the second output clock on the basis of the subsidiary comparison signal so that the phase of the second output clock coincides with that of the first output clock.
According to still another aspect of this invention, a clock producing method comprising the steps of producing a first output clock according to a first reference clock by the use of a first phase locked loop, producing a second output clock according to a second reference clock by the use of a second phase locked loop, comparing phase of the first output clock with that of the second output clock to produce a comparison signal representing phase difference between the first and the second output clocks, and adjusting phase of the second output clock according to the comparison signal by the use of a digital filter included in the second phase locked loop so as to reduce said phase difference.